Introduction:
VHDL stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language. U.S. Department of Defense developed VHDL in 70’s and 80’s with ADA as its root. IEEE adopted VHDL as a standard in 1987. VHDL is now used to describe most of the digital systems. We can design hardware in a VHDL IDE, for FPGA implementation, to produce the RTL schematic of the desired circuit. Then the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate test-bench. To generate an appropriate test-bench for a particular circuit or VHDL code, the inputs have to be defined correctly. When the VHDL model is written in FPGA, the model is transformed to actual hardwired components rather than just a programming language loaded to a processor. Hence rather than program being executed, we run the model in hardwired form.
FPGA design and programming
To define the behavior of the FPGA, we write a hardware description language (HDL) or make a schematic design. The HDL form is more suited to work with large structures because it's possible to just specify them numerically rather than having to draw every piece by hand. However, schematic entry can allow for easier visualization of a design. Then, using an electronic design automation tool, a technology-mapped netlist is generated. The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA Company’s proprietary place-and-route software. The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies. Once the design and validation process is complete, the binary file generated is used to (re)configure the FPGA. This file is transferred to the FPGA/CPLD via a serial interface (JTAG) or to an external memory device like an EEPROM. Advantages of VHDL:
1. It allows us to model the behavior of the required system and simulate it before synthesis tools translates the design into real hardware (gates and wires).
2. VHDL unlike most of the programming language allows us to write concurrent statements. These concurrent statements are executed in parallel. This increases the processing speed.
3. VHDL project is multipurpose. Being created once, a calculation block can be used in many other projects. However, many formational and functional block parameters can be tuned (capacity parameters, memory size, element base, block composition and interconnection structure).
4. VHDL project is portable. Being created for one element base, a computing device project can be ported on another element base, for example VLSI with various technologies.
VHDL Constructs
Entity: An entity is the most basic building block in a design. The uppermost level of the design is the top-level entity. If the design is hierarchical, then the top-level description will have lower-level descriptions contained in it. These lower-level descriptions will be lower-level entities contained in the top-level entity description.
Architecture: All entities that can be simulated have an architecture description. The architecture describes the behavior of the entity. A single entity can have multiple architectures.
Configuration: A configuration statement is used to bind a component instance to an entity-architecture pair.
Package: A package is a collection of commonly used data types and subprograms used in a design.
Driver: This is a source on a signal. If a signal is driven by two sources, then when both sources are active, the signal will have two drivers.
Bus: The term “bus” usually brings to mind a group of signals or a particular method of communication used in the design of hardware.
Attribute: An attribute is data that are attached to VHDL objects or predefined data about VHDL objects.
Generic: A generic is VHDL’s term for a parameter that passes information to an entity. For instance, if an entity is a gate level model with a rise and a fall delay, values for the rise and fall delays could be passed into the entity with generics.
Process: A process is the basic unit of execution in VHDL. All operations that are performed in a simulation of a VHDL description are broken into single or multiple processes.
VHDL code Structure:
VHDL code structure consists of library declarations, entity and architecture defining the behavior of the entity.
Library: It is the collection of commonly used codes. Placing the codes inside the library allows us to frequently use them anywhere possible. The code is usually written in the form of FUNTIONS, POCEDURES, COMPONENTS, CONSTANTs or TYPES which are placed inside a PACKAGE. Library is declared using the following statement.
LIBRARY library_name;
USE library_name.package_name.package_parts;
Entity: Entity is the list of all the input output port and its specifications. It consists of the following format:
Architecture: It is a description of the behavior of the entity. Its syntax is as follows:
