Specifications
1. RAM: 32*8 bits of RAM
2. Data Bus: 8 bit
3. User Visible registers: A, B, C, D
4. Control and status registers: MAR, MBR, IR, PC, TEMP
5. ALU: 8 bit, performs Addition, complementing and logical NAND operation
6. Flag: Zero, carry
The block diagram of the microprocessor is shown below:
The microprocessor is based on RISC approach. Hence it supports minimum number of instructions.
Instruction set
Instruction is 8 bit. The first 3 bits denote the type of instruction. The last 2 bits give the register address.
The instruction set is as follows
1. SFA memory: Store from register A to given memory address
2. STA memory: Store to register A from given memory address
3. JMP memory: Performs unconditional jump to the given memory address
4. ADD A, R: Performs addition between the given register and register A and stores in register A
5. CMP: Complements the contents of register A
6. NAND A, R: Performs logical NAND between register A and given register contents
7. MVI A, Data: performs immediate addressing
8. MOV A, R: Moves the data from register A to given register
The instruction decoder and the timing generator is shown below:
The combinational logic used to generate the required signal for the different latches present in the registers, ALU was drawn based on the micro-instruction analysis. Which I’ll add shortly.
The combinational logic thus designed is as shown below:
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